FPGAs may be used to implement large systems that include millions of gates and megabits of embedded memory. The process flow for implementing a system onto a target FPGA device includes performing synthesis, placement, and routing. Synthesis involves generating a logic design of the system to be implemented by a target device and mapping the logic design onto resources on the FPGA that will implement the logic design. The tasks of performing synthesis, placement, and routing can be both challenging and time consuming. In order to implement a system with the limited resources on an FPGA, several iterations are often required to determine an acceptable logic design and appropriate mapping of resources on the FPGA to components in the logic design. The complexity of large systems often requires the use of EDA tools to manage and optimize their design onto physical target devices. EDA tools have been used by designers to perform the time consuming task of synthesis, placement, and routing of components onto physical devices.
Traditional EDA tools typically operate only on individual cones of logic to map a network of logic gates in the cones of logic to a network of look up tables that are programmed to perform an equivalent functionality. These EDA tools do not examine how individual cones of logic relate to other cones of logic in a logic design for optimization purposes. When a system requires the use of resources that exceed the offering of a particular FPGA platform, these EDA tools may fail to generate an acceptable mapped logic design.
Thus what is needed is an effective method and apparatus for performing synthesis to improve the density on FPGAs.